4 Inch Silicon Wafer
Manufacturing process of silicon wafer Slicing follows the process of cutting the ingot into thin wafer slices. We used cutting-edge wire and I.D. saws that are operated by experienced and well-trained operators to produce high quality wafers. The techniques to achieve thin wafers with low kerf...
Manufacturing process of silicon wafer
Slicing follows the process of cutting the ingot into thin wafer slices. We used cutting-edge wire and I.D. saws that are operated by experienced and well-trained operators to produce high quality wafers. The techniques to achieve thin wafers with low kerf loss are applied, which help to ensure wafer flatness and total thickness variation (TTV) is controlled to minimum.
After slicing process, We used edge grinding technology to create rounded edges on each wafer. The purpose of this step is to minimize edge chipping, breakage and thermal induced slip in the subsequent customer's thermal processes. Based on different Epi thickness and/or processes, an optimized edge profile and length can be made with specific customer specifications.
Both acid and caustic etching are available according to customer's requirements. The damaged layers caused by the previous processes are removed during etching process. We can also provide a residual damage layer during the caustic etching process for backside gettering purposes. Special shape control can be achieved with state-of-the-art etching machines and techniques.
Polishing techniques have a big impact on the outcome of the wafer's surface, which is why We use sophisticated polished and a rigorous inspection process to produce world-class silicon wafers. Wafer Works is able to perform tight roughness wafer surface.
The cleaning process removes surface metals as well as micro particles away from wafer surface. Our engineering group has conducted various experiments that help to modify our cleaning process to perfection stage.
Prime polished wafers are transferred to the epitaxial furnace area inside the clean room. Epitaxy is a process that grows a thin, ultra-pure layer of silicon on the polished surface of a silicon wafer substrate. Polished wafers are loaded into single slice, or multiple slice capacity, "epi" reactor. The recipe, or customer specification, is programmed for that machine's run (cycle). Trichlorosilane gas is injected at a high-temperature as the wafer spins in the reactor. The gas flows over the top resulting in the silicon atoms adhering to the crystalline wafer structure. This "epi" layer is designed to have different compositional and electrical properties from the underlying wafer, tailored to the specific demands of the device.
In order to supply defect-free products to our customers, we have conducted visual inspection on each wafer in the drak room with the assistance of the auxiliary light sources. After the wafer has undergone polishing and cleaning procedures, we use advanced equipment and cutting-edge technology to accurately measure the wafer's resistivity, thickness, TTV, STIR, bow and warp, etc. according to customer's requirements.To ensure we are delivering high quality wafers to customers, we use precise, state-of-the-art machines that accurately measure particle count on the wafer's surface before packaging.
The wafers are desiccated with a nitrogen purge to evacuate humidity down, tape sealed, double bagged (PE + Aluminum Bag), and then vacuum packed in a class 10 clean room environment.